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1 ? fn6251.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners. preliminary isl59531 16x16 video crosspoint with differential inputs the isl59531 is a 16x16 integrated video crosspoint switch matrix with differential input and on-screen display (osd) insertion. the isl59531 is ideal for routing video signals in security and video-on-dem and systems. this device operates from a single +5v supply. any output of the 16 video inputs cable can be switched to any of the 16 outputs. osd information can be inserted into any output through an internal, dedicated fast 2:1 mux (15ns switching times) located before the output buffer. also, any input can be broadcast to all 16 outputs. each output can be tri-stated and its gain set to +1 or +2 through the spi interface. the isl59531 offers a -3db signal bandwidth of 320mhz. the differential gain and differential phase of 0.025%, along with 0.1db flatness out to 50mhz, making the isl59531 suitable for many video applications. the switch matrix configuration and output buffer gain are programmed through an spi/qspi?-compatible three-wire serial interface. the isl59531 interface is set up to facilitate both fast updates and initializati on. on power-up, all outputs are initialized in the disabled state to avoid output conflicts within the user system. the isl59531 has si ngle-supply signal operation. it can accommodate input common mode voltages from 0v to 3.5v and 0v to 4v at the outputs. the isl59531 is available in a 356-pin bga package and specified over an extended - 40c to +85c temperature range. the isl59530 is a single-ended input version of this device. for capacitor-coupled applications, the isl59530 inputs include a clamp circuit that restores the input level to an externally applied reference. features ? 16x16 non-blocking switch with differential inputs and outputs ? operates from a single +5v supply ? output gain switchable +1 or +2 ? spi digital interface ? tri-state output ? -90db isolation at 6mhz ? 0.025%/0.05 dg/dp ? pb-free plus anneal available (rohs compliant) applications ? security camera switching ?rgb routing ? hdtv routing ordering information part number tape & reel package pkg. dwg. # ISL59531IKZ (see note) -356-pin bga (pb-free) v356.27x27 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet march 21, 2006
2 fn6251.0 march 21, 2006 pinout isl59531 (356-pin bga) top view 20 5 234 678910111213141516171819 1 a b c d e f g h j k l m n p r t u v w y in12 in13 in14 in15 over15 over14 out13 out12 inb12 inb13 inb14 inb15 out15 out14 over13 over12 vover15 vover14 vover13 vover12 in11inb11vlogicvsvsvsvsvsvsvsvsvsvsvsvsvsvsvover11out11over11 vs vs in10 inb10 vs gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vs vover10out10 over10 sout vs gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vs in9 inb9 reset vs vs vover9 over9 out9 senb vs vs in8 inb8 clock vs vs vover8 over8 out8 sdi vs vs in7 inb7 ref vs vs vover7 out7 over7 vs vs in6 inb6 vs vs vover6 out6 over6 vs vs in5 inb5 vs vs vover5 over5 out5 vs vs vs vs vs vs vs vs vs vs vs vs vs in4 inb4 spare0 diode vover0 vover1 vover2 vover4 over4 out4 spare1 vover3 inb3 inb2 inb1 inb0 over0 over1 out2 out3 in3 in2 in1 in0 out0 out1 over2 over3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd pad name "gnd" is the same as package or ball name "ground" or "g" pad name "vs" is the same as package or ball name "power" or "p" pad x, y is from pad center. all pads are 70 by 70 = empty location (unpopulated) = ballgrid isl59531
3 fn6251.0 march 21, 2006 absolute maxi mum ratings (t a = 25c) supply voltage between v s and gnd. . . . . . . . . . . . . . . . . . . . 5.5v maximum continuous output current . . . . . . . . . . . . . . . . . . . 40ma ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications v s = 5v parameter description condition min typ max unit v s supply range 4.5 5.5 v v d digital supply establishes seri al output high level 1.2 5.5 v a v gain a v = 1, r l = 500 ? 0.9711.03v/v a v = 2, r l = 150 ? 1.9422.06v/v gm gain matching (to average of all other outputs) a v = 1 -1.5 1 1.5 % a v = 2 0.5 1.0 % v in input voltage range a v = 1 0 3.5 v v out output voltage range a v = 2, r l = 150 ? 04.0v i b input bias current -10 -5 0 a v os output offset voltage a v = 1 -25 0 25 mv a v = 2 -70 0 70 mv i out output current sourcing, r l = 10 ? to gnd 60 100 ma sinking, r l to 2.5v 25 35 ma psrr power supply rejection ratio 80 db i s supply current enabled, all outputs enable, no load current 312 375 ma enable, all outputs disable, no load current 140 ma disabled 0.8 1.1 ma supply current per output channel 7 ma ac electrical specifications parameter description condition min typ max unit bw -3db 3db bandwidth v out = 200mv p-p , a v = 2 320 mhz bw 0.1db 0.1db bandwidth v out = 200mv p-p , a v = 2 50 mhz sr slew rate v out = 2v p-p , a v = 2 360 520 v/s t s settling time to 0.1% v out = 2v p-p , a v = 2 12 ns glitch switching glitch, peak a v = 1 40 mv t over overlay delay time beginning of output transition 6 ns dg diff gain a v = 2, r l = 150 ? 0.025 % dp diff phase a v = 2, r l = 150 ? 0.05 xt hostile crosstalk 6mhz -85 db v n input noise voltage 42 nv/ hz isl59531
4 fn6251.0 march 21, 2006 pin descriptions name number description inb2 w4 complementary input in2 y4 input inb3 w2 complementary input in3 y2 input ref m3 output reference gnd gnd ground sdi l3 serial data input vs vs power supply inb4 v2 complementary input in4 v1 input inb5 t2 complementary input in5 t1 input vs vs power supply gnd gnd ground inb6 p2 complementary input in6 p1 input inb7 m2 complementary input in7 m1 input clock k3 serial data clock vs vs power supply senb j3 serial enable-inverted gnd gnd ground inb8 k2 complementary input in8 k1 input inb9 h2 complementary input in9 h1 input vs vs power supply gnd gnd ground inb10 f2 complementary input in10 f1 input inb11 d2 complementary input in11 d1 input reset h3 reset input vs vs power supply sout g3 serial data output gnd gnd ground inb12 b1 complementary input in12 a1 input inb13 b3 complementary input in13 a3 input input test bar none manufacturing test pin - leave open gnd gnd ground gnd gnd ground vs vs power supply vs vs power supply vlogic d3 logic power supply for serial output driver inb14 b5 complementary input in14 a5 input inb15 b7 complementary input in15 a7 input vsl vs power supply vgl gnd ground vs vs power supply gnd gnd ground over15 a11 overlay logic control vover15 c11 overlay analog input out15 b11 output over14 a13 overlay logic control vover14 c13 overlay analog input out14 b13 output gnd gnd ground vs vs power supply out13 a15 output vover13 c15 overlay analog input over13 b15 overlay logic control out12 a17 output vover12 c17 overlay analog input over12 b17 overlay logic control gnd gnd ground out test 3 none manufacturing test pin - leave open vs vs power supply over11 d20 overlay logic control vover11 d18 overlay analog input out11 d19 output over10 f20 overlay logic control vover10 f18 overlay analog input out10 f19 output pin descriptions (continued) name number description isl59531
5 fn6251.0 march 21, 2006 gnd gnd ground vs vs power supply out9 h20 output vover9 h18 overlay analog input over9 h19 overlay logic control out8 k20 output vover8 k18 overlay analog input over8 k19 overlay logic control out test 2 none manufacturing test pin - leave open gnd gnd ground vs vs power supply over7 m20 overlay logic control vover7 m18 overlay analog input out7 m19 output over6 p20 overlay logic control vover6 p18 overlay analog input out6 p19 output gnd gnd ground vs vs power supply out5 t20 output vover5 t18 overlay analog input over5 t19 overlay logic control out4 v20 output vover4 v18 overlay analog input over4 v19 overlay logic control vs vs power supply out test 1 none manufacturing test pin - leave open gnd gnd ground over3 y16 overlay logic control vover3 v16 overlay analog input out3 w16 output over2 y14 overlay logic control vover2 v14 overlay analog input out2 w14 output vs vs power supply gnd gnd ground out1 y12 output vover1 v12 overlay analog input over1 w12 overlay logic control out0 y10 output pin descriptions (continued) name number description vover0 v10 overlay analog input over0 w10 overlay logic control vs vs power supply out test 0 none manufacturing test pin - leave open gnd gnd ground in0 y8 input inb0 w8 complementary input in1 y6 input inb1 w6 complementary input diode v9 anode of a ground-connected diode: useful for measuring die temperature vs vs power supply gnd gnd ground vs vs power supply gnd gnd ground spare0 v6 not assigned-do not connect spare1 v5 not assigned-do not connect pin descriptions (continued) name number description isl59531
6 fn6251.0 march 21, 2006 typical performance curves figure 1. frequency response - various c l , a v = 1, mux mode figure 2. frequency response - various c l , a v = 2, mux mode figure 3. frequency response - various r l , a v = 1, mux mode figure 4. frequency response - various r l , a v = 2, mux mode figure 5. frequency response - overlay input, a v = 1 figure 6. frequency response - overlay input, a v = 2 v s =+5v a v = 1 r l = 100 ? input_ch 0 output_ch 0 0pf 4.7pf 15pf 10pf v s =+5v a v = 2 r l = 100 ? input_ch 0 output_ch 0 15pf 10pf 4.7pf 0pf v s =+5v a v = 1 c l = 0pf input_ch 0 output_ch 0 50 ? 150 ? 500 ? 1.03k ? v s =+5v a v = 2 c l = 0 input_ch 0 output_ch 0 1.03k ? 500 ? 50 ? 150 ? overlay mode a v = 1 r l = 100 ? c l =0pf input_ch 15 output_ch 31 overlay mode a v = 2 r l = 100 ? c l =0pf input_ch 15 output_ch 15 isl59531
7 fn6251.0 march 21, 2006 figure 7. frequency response - various c l , a v = 1, broadcast mode figure 8. frequency response - various c l , a v = 2, broadcast mode figure 9a. frequency response - various r l , a v = 1, broadcast mode figure 10. frequency response - various r l , a v = 2, broadcast mode figure 11. crosstalk - a v = 1 figure 12. crosstalk - a v = 2 typical performance curves (continued) v s =+5v a v = 1 r l = 100 ? input_ch 0 output_ch 0 15pf 10pf 4.7pf 0pf v s =+5v a v = 2 r l = 100 ? input_ch 0 output_ch 0 15pf 4.7pf 0pf 10pf v s =+5v a v = 1 c l = 0pf input_ch 0 output_ch 0 50 ? 150 ? 1.03k ? 503 ? v s =+5v a v = 2 c l = 0pf input_ch 0 output_ch 0 50 ? 1.03k ? 503k ? 150k ? a v = 1 r l = 100 ? c l = 0 all hostile input_ch0 output_ch31 adjacent input_ch14 output_ch15 a v = 2 r l = 100 ? c l = 0 all hostile input_ch0 output_ch15 adjacent input_ch14 output_ch15 isl59531
8 fn6251.0 march 21, 2006 figure 13. harmonic distortion vs frequency figure 14. harmonic distortion vs v out_p-p figure 15. disable output impedance figure 16. enable output impedance figure 17. rise time - a v = 1 figure 18. fall time - a v = 1 typical performance curves (continued) v s =+5v a v =2 r l =100 ? input_ch 0 output_ch 0 v op-p =2v 2nd hd 3rd hd thd v s =+5v a v =2 r l =100 ? input_ch 0 output_ch 0 frequency = 1mhz thd 2nd hd 3rd hd mux mode a v = 1 r l = 100 ? input_ch 15 output_ch 15 rise time 2.35ns mux mode a v = 1 r l = 100 ? input_ch 15 output_ch 15 fall time 2.65ns isl59531
9 fn6251.0 march 21, 2006 figure 19. rise time - a v = 2 figure 20. fall time - a v = 2 figure 21. rising slew rate - a v = 1 figure 22. falling slew rate - a v = 1 figure 23. rising slew rate - a v = 2 figure 24. falling slew rate - a v = 2 typical performance curves (continued) mux mode a v = 2 r l = 100 ? input_ch 15 output_ch 15 rise time 2.19ns mux mode a v = 2 r l = 100 ? input_ch 15 output_ch 15 fall time 2.35ns mux mode a v = 1 r l =100 ? input_ch 15 output_ch 15 slew rate 448v/s mux mode a v = 1 r l =100 ? input_ch 15 output_ch 15 slew rate -436v/s mux mode a v = 2 r l =100 ? input_ch 15 output_ch 15 slew rate 531v/s mux mode a v = 2 r l =100 ? input_ch 15 output_ch 15 slew rate -511v/s isl59531
10 fn6251.0 march 21, 2006 figure 25. overlay switch turn-on delay time figure 26. overlay switch turn-off delay time figure 27. differential gain, a v = 2 figure 28. differential phase, a v = 2 figure 29. differential gain, a v = 2 figure 30. differential phase, a v = 2 typical performance curves (continued) overlay logic input output overlay logic input output a v = 2 r l = 150 ? input_ch 15 output_ch 15 osc = 40mv a v = 2 r l = 150 ? input_ch 15 output_ch 15 osc = 40mv a v = 2 r l = 150 ? input_ch 15 output_ch 15 osc = 40mv a v = 2 r l = 150 ? input_ch 15 output_ch 15 osc = 40mv isl59531
11 fn6251.0 march 21, 2006 figure 31. differential gain, a v = 1 figure 32. differential phase, a v = 1 figure 33. differential gain, a v = 1 figure 34. differential gain, a v = 1 figure 35. differential gain, a v = 2 figure 36. differential phase, a v = 2 typical performance curves (continued) a v = 1 r l = 150 ? input_ch 15 output_ch15 osc = 40mv a v = 1 r l = 150 ? input_ch 15 output_ch 15 osc = 40mv a v = 1 r l = 150 ? input_ch 15 output_ch 15 osc = 40mv a v = 1 r l = 150 ? input_ch 15 output_ch 15 osc = 40mv a v = 2 r l = 150 ? input_ch 00 output_ch 15 osc = 40mv a v = 2 r l = 150 ? input_ch 00 output_ch 15 osc = 40mv isl59531
12 fn6251.0 march 21, 2006 figure 37. differential gain, a v = 2 figure 38. differential phase, a v = 2 figure 39. differential gain, a v = 1 figure 40. differential phase, a v = 1 figure 41. differential gain, a v = 1 figure 42. differential phase, a v = 1 typical performance curves (continued) a v = 2 r l = 150 ? input_ch 00 output_ch 15 osc = 40mv a v = 2 r l = 150 ? input_ch 00 output_ch 15 osc = 40mv a v = 1 r l = 150 ? input_ch 00 output_ch 15 osc = 40mv a v = 1 r l = 150 ? input_ch 00 output_ch 15 osc = 40mv a v = 1 r l = 150 ? input_ch 00 output_ch 15 osc = 40mv a v = 1 r l = 150 ? input_ch 00 output_ch 15 osc = 40mv isl59531
13 fn6251.0 march 21, 2006 figure 43. differential gain, overlay, a v = 2 figure 44. differential phase, overlay, a v = 2 figure 45. differential gain, overlay, a v = 1 figure 46. differential phase, overlay, a v = 1 typical performance curves (continued) a v = 2 r l = 150 ? input_ch 00 output_ch 00 osc = 40mv a v = 2 r l = 150 ? input_ch 00 output_ch 00 osc = 40mv a v = 1 r l = 150 ? input_ch 00 output_ch 00 osc = 40mv a v = 1 r l = 150 ? input_ch 00 output_ch 00 osc = 40mv isl59531
14 fn6251.0 march 21, 2006 3db bandwidth, mux mode, a v = 1, r l = 100 ? [mhz] input channels 0123456789101112131415 output channels 0 255 229 229 210 222 221 224 190 169 152 233 190 212 189 207 166 1 244 217 180 168 193 160 2 257 235 186 171 204 169 3 264 217 183 175 219 171 4 255 220 174 177 202 167 5 253 218 176 177 237 173 6 247 226 171 178 157 170 7 253 227 235 218 223 228 230 174 184 163 240 223 219 217 211 178 8 255 236 240 239 223 236 231 175 187 168 241 242 222 235 213 183 9 241 210 169 188 165 182 10 235 236 168 186 230 185 11 223 207 164 188 225 186 12 220 209 161 192 205 185 13 211 214 160 192 224 189 14 199 212 160 194 197 193 15 193 217 207 202 185 216 186 222 197 177 225 217 198 223 197 238 3db bandwidth, mux mode, a v = 2, r l = 100 ? [mhz] input channels 0123456789101112131415 output channels 0 295 316 290 397 384 405 395 220 288 240 299 250 385 234 396 188 1 268 290 211 183 291 183 2 277 300 216 192 289 196 3 279 408 213 196 392 196 4 269 391 201 192 402 192 5 263 407 201 196 298 200 6 259 404 196 196 283 200 7 263 411 307 402 387 412 398 201 205 407 307 402 387 413 398 211 8 262 407 308 402 383 412 394 203 212 411 300 403 385 415 394 216 9 253 388 194 210 410 214 10 253 417 194 215 293 216 11 246 385 187 213 412 217 12 241 412 184 216 391 225 13 236 272 182 220 419 225 14 233 279 178 220 396 230 15 227 274 244 396 367 407 230 183 223 324 276 400 379 413 385 293 isl59531
15 fn6251.0 march 21, 2006 3db bandwidth, broadcast mode, a v = 1, r l = 100 ? [mhz] input channels 0123456789101112131415 output channels 0 215 198 195 183 184 188 172 178 151 145 157 145 140 146 144 158 1 214 195 174 152 144 158 2 210 188 171 153 147 159 3 212 178 171 157 143 164 4 206 174 169 157 150 164 5 203 177 165 159 161 164 6 201 156 163 159 151 164 7 204 187 182 170 170 175 160 167 167 156 168 157 151 158 154 170 8 204 187 183 172 171 176 161 167 171 160 172 160 155 161 159 175 9 202 157 164 170 160 174 10 196 170 160 169 169 178 11 194 161 157 171 160 174 12 193 162 156 171 156 178 13 191 170 151 174 164 178 14 189 172 151 175 162 178 15 187 173 167 157 155 161 149 153 178 167 179 167 160 166 164 181 3db bandwidth, broadcast mode, a v =2, r l = 100 ? [mhz] input channels 0123456789101112131415 output channels 0 234 216 209 199 204 205 190 196 169 160 172 162 158 163 161 178 1 232 215 193 169 161 178 2 228 204 189 171 164 178 3 229 196 191 175 163 182 4 223 193 186 177 168 183 5 219 192 183 177 177 183 6 217 174 181 178 167 183 7 220 204 198 189 190 192 175 183 184 173 184 174 169 174 172 189 8 220 205 199 190 191 193 177 184 187 178 188 178 173 178 178 193 9 218 174 181 188 178 193 10 220 185 176 186 187 192 11 212 179 174 188 177 192 12 211 179 174 192 176 195 13 209 187 170 192 181 195 14 208 191 167 194 181 196 15 205 191 184 172 171 176 160 166 197 185 195 184 179 185 182 198 isl59531
16 fn6251.0 march 21, 2006 block diagram general description the isl59531 is a 16x16 integrated video crosspoint switch matrix with differential input and output buffers and on- screen display (osd) insertion. this device operates from a single +5v supply. any output can be switched to any of the 16 input video signal sources and osd information through an internal, dedicated fast 2: 1 mux located before the output buffer. also, any one input can be broadcast to all 16 outputs. each output x is defined as: voutx = avx*(inx-inbx+ref) where avx = 1, or avx = 2. note that all ref?s are common between channels and must be externally well buffered and/or bypassed. the isl59531 offers a -3db signal bandwidth of 320mhz. the differential gain and differential phase of 0.025% and 0.05 respectively, along with 0.1db flatness out to 50mhz. the switch matrix configuration and output buffer gain are programmed through an spi/q spi?-compatible, three-wire serial interface. the isl59531 interface is set up to facilitate both fast updates and initializati on. on power-up, all facilities are initialized in the disabled state to avoid output conflicts within the user system. digital interface the isl59531 uses a simple 3-wire spi compliant digital interface to program the output s. the isl59531 can support the clock rate up to 5mhz. serial interface the isl59531 is programmed through a three-wire serial interface. the start and stop conditions are defined by the ena signal. while the ena is low, the data on the sdi (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the sclk (serial clock) signal. the lsb (bit 0) is loaded first and the msb (bit 15) is loaded last (see table 1). after the full 16-bit data has been loaded, the ena is pulled high and the addressed output channel is updated. the sclk is disabled internally when the ena is high. the sclk must be low before the ena is pulled low. the serial timing diagram and parameters table show the timing requirements fo r three-wire signals. overn vovern output enable vs+ sdi ena clk sdo power-on power-on v in 0 v in 15 switch matrix - + - + spi interface, register 16 overlay input 16 logic control a v +1, +2 16 inputs 16 outputs ref isl59531
17 fn6251.0 march 21, 2006 serial timing diagram programming model the device has power-on reset that disables outputs, disables te st mode, and turns off analog currents. to start up the device the control word is sent: it is important to always program control bits 2-8 as zeros to avoid activating test modes designed for device manufacturing.th e clamp bit activates the input clamp and bleed current sink and works only in the single-ended version. to enable individual outputs, the output enable control word is sent. there are 16 enables to set; this is done with serial wor ds controlling four at a time. the out put enable control word format is: the o x bits represent output enables of eight i ndividual registers. the n1 and n0 bits represent a two bit binary number which is used in setting n = 2 n1n0 . for instance, to access the control bit of the 5th output enable, we send the word: individual output enables are ended with the control r egister?s common output enable bit and the power on bit. table 1. serial timing parameters parameter recommended operating range description t 200ns clock period t he 20ns ena hold time t se 20ns ena setup time t hd 20ns data hold time t sd 20ns data setup time t w 0.50 * t clock pulse width ena sclk t r t w t he t se t f t sd t hd t b0 b1 b2 b12-b2 b14 b15 sdi lsb msb t load msb first, lsb last t e table 2. control word format b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 - - - - 0 --0 0 0 0 0 0 power on common output enable table 3. output enable format b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 - - - n1 n0 - o n+3 -o n+2 -o n+1 -o n table 4. output enable word of 2nd group of outputs b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 001 - - - 01 -o 7- o 6 -1-o 4 isl59531
18 gain setting the gain of each output may be set to 1 or 2 using the gain set word. it is in the same format as the output enable control wor d: input to output selection individual outputs receive their input selection choice using the input/output control word. its format is: for a given binarily selected output, as s pecified by the o's, an input channel is a ssigned by the binarily selected i's. sixte en transmissions of the input/outpu t control words will be required to set up all outputs. note that b8 and b0 must be logic 0. broadcast mode the broadcast mode routs one input to all 16 outputs. it has a memory bit that remembers its state. the configuration of input/output assignments that existed before setting broadcast m ode is kept in memory and when broadcast mode is disabled the previous configuration is restored. t he broadcast control word format is: eb sets or resets the broadcast mode memory bit. the i's binarily select the input channel to be broadcast to all outputs. note that b8 must be logic 0. bandwidth considerations wide frequency response (high bandwidth) in a video system means better video resolution. four sets of frequency response curves are shown in figure 47. depending on the switch configurations, one can get between 250mhz to 350mhz bandwidth. a short discussion of the trade-offs follows?inclu ding matrix configuration, output buffer gain selection, channel selection, and loading. figure 47. frequency response for various modes in multiplexer mode, the inpu t only drives one output channel, while in broadcast mode the same input drives all 16 outputs. the parasitic capacitance of all 16 channels loads down the input and reduces bandwidth in broadcast mode. in addition, output buffer gain of +2 has higher bandwidth than gain of +1 due to internal device compensation. therefore, the highest bandwidth set-up is multiplexer mode and output buffer gain of +2. the relative location of the input and output channel also has significant impact on the device bandwidth. again this is due to the layout of the device . when the input and output channels are further away, there are additional parasitics as a result of the distance and lower bandwidth results. the bandwidth does not change significantly with resistive loading as shown in figure 3 in the typical performance curves. however, it does change greatly with capacitance loading, figure 4 in typical performance curves. this is most significant when laying out the pcb. if the pcb trace between the output of the crosspoint switch and the back termination resistor is not minimized, additional parasitic capacitance severely distorts the frequency response. to emphasize how critical the pc b layout is to performance, let?s compare the two boards presented in figures 48 and 49. figure 48 shows a larger engineering evaluation board where the termination resistor is far away from the device because of the use of a socket. the board in figure 48 is a demoboard without the socket. the parasitic capacitance of the demoboard is about 2.7pf less. table 5. gain set format b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 - - - n1 n0 - g n+3 -g n+2 -g n+1 -g n table 6. input/output word b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 000i 3 i 2 i 1 i 0 0- - -o 3 o 2 o 1 o 0 0 table 7. broadcast word b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 011i 3 i 2 i 1 i 0 0-------eb 1 10 100 1000 2 0 -2 -4 -6 -8 -10 normalized gain [db] frequency [mhz] mux, av = 2 mux, av = 1 broadcast, av = 1 broadcast, av = 2 isl59531
19 figure 48. engineering evaluation board figure 49. customer demoboard to prove that the parasitic capacitance is the largest contributor to the difference in bandwidth of the two boards, we added 2.7pf at the output of the demoboard. figure 50 shows the similarity in frequency response of the engineering evaluation board alongside the demoboard piggybacked with 2.7pf. linear operating region in addition to bandwidth, one must also be very careful with operating the device at its line ar operating region. figure 50 shows differential gain curve. the isl59534 is a single supply 5v device with its linear region is between 0.1 and 2v. figure 50. differential gain response power dissipation and thermal resistance with a large number of switches, it is possible to exceed the 150c absolute maximum ju nction temperature under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the crosspoint switch in a safe operating area. the maximum power dissipation allowed in a package is determined according to: where: ?t jmax = maximum junction temperature = 125 c ?t amax = maximum ambient temperature = 85 c ? ja = thermal resistance of the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the load, or: pd max t jmax t amax ? ja -------------------------------------------- - = pd max v s i smax v s v outi ? () i1 = n v outi r li ----------------- + = isl59531
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com where: ?v s = supply voltage = 5v ?i smax = maximum quiescent supply current = 375ma ?v out = maximum output voltage of the application = 2v ?r load = load resistance tied to ground = 150 ? n = 1 to 15 channels the reqired ja to dissipate 2.52w is: table 8 shows ja thermal resistance results for various airflows. at the thermal resistance equation shows, the required thermal resistance depends on the maximum ambient temperature. table 8. ja thermal resistance [ c/w] airflow [lfm] 0 250 500 750 18 14.3 13.0 12.6 pd max v s i smax v s v outi ? () i1 = n v outi r li ----------------- + 2.52w = = ja t jmax t amax ? pd max -------------------------------------------- - 15.9 c/w () = = isl59531
21 356 ld pbga package isl59531

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